Hybrid Senior Physical Design Application Engineer

Posted 11 hours ago

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About the role

  • Senior Applications and Solutions Engineer providing technical support for Intel Foundry Services to ensure successful ASIC tape-outs. Drive customer success through advanced CMOS process implementation and design flow optimization.

Responsibilities

  • Provide comprehensive technical support to Intel Foundry Services customers on PDKs, digital reference flows, and digital design signoff methodologies
  • Support and deliver ASIC/Digital tool/flow/methodology solutions using Cadence tool suites to address customer issues and ensure successful tape-outs
  • Drive customer success through expert guidance on advanced CMOS process implementation
  • Drive quality improvements in design kits and documentation through ASIC design reference flow validation and comprehensive documentation review
  • Create application notes, technical content, and deliver training presentations to customers and internal teams
  • Develop and optimize digital design implementation flows for advanced CMOS processes

Requirements

  • US Citizenship required
  • Ability to obtain a US Government Security Clearance
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or STEM-related field of study
  • 4+ years of experience with advanced CMOS processes (22 nm and below)
  • 3+ years of experience in ASIC physical design implementation and/or ASIC design signoff (SoC/ASIC)
  • 3+ years of experience in one of the following scripting languages (i.e. Python, Perl, Tcl, shell scripting)

Benefits

  • Competitive compensation
  • Stock bonuses
  • Health, retirement, and vacation benefits

Job title

Senior Physical Design Application Engineer

Job type

Experience level

Senior

Salary

$122,440 - $232,190 per year

Degree requirement

Bachelor's Degree

Location requirements

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