Memory Systems Engineer at Kandou focusing on DRAM subsystem design and FPGA prototyping in Switzerland. Collaborating on architectural performance simulations and validation plans for memory controllers.
Responsibilities
Architectural performance simulations using application traces or synthetic workloads to quantify the effects of various memory subsystems
FPGA prototyping of memory subsystems in the lab for functional and performance validation.
Use of off shelf FPGA boards is acceptable.
Analysis of configurations of memory controllers and their impact on computer system performance
Participate in SoC architecture design and analysis particularly being responsible for memory controllers
Assist the engineering team in formulating and executing design verification and validation plans around DRAM controller & memory
Requirements
Must have designed a DRAM controller and tested it using either FPGA or ASICs
DRAM performance modeling and characterization experience in either industrial or academic setting
Correlate key application performance to DRAM subsystem capabilities either by gathering traces or by directed testing techniques in the lab.
Key applications may be any one of databases, machine learning or search
Working knowledge of Linux kernel with a strong preference for some development or testing work
Architectural simulations of computer systems with a particular emphasis on DRAM subsystems
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