Lead Micro-Architect developing advanced memory controllers at Samsung Austin Research and Development Center. Focus on high-performance computing devices with significant influence over memory-controller micro-architecture.
Responsibilities
Lead the design and development of Samsung's advanced memory controller (LPDDR5, LPDDR6, PIM, and beyond (DDR5, GDDR7, HBM4).
Assume ownership and exert significant influence over the entire memory-controller micro-architecture, including RTL design and performance/power optimization.
Translate innovative concepts into cutting-edge, next-generation memory technologies.
Collaborate with cross-functional teams to ensure design functionality and resolve implementation challenges.
Ensure design quality through LINT, CDC, ECO flows, power analysis, and other methodologies.
Requirements
20+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 18+ years of experience with a Master’s Degree, or 16+ years of experience with a PhD
Proven experience in memory controller micro-architecture and RTL design, owning all sub-blocks of custom memory controller designs.
Deep expertise in multiple memory technologies, such as LPDDR4/5/6, PIM, DDR, GDDR, and HBM.
Strong knowledge of JEDEC memory standards and working knowledge of DDR PHY.
Demonstrated success in driving architecture through RTL design for high-performance digital systems.
Strong expertise in Verilog and ASIC design flow, including RTL design, verification, synthesis, timing analysis, and ECO.
Proficiency in scripting languages (Perl, Python) to support design and automation.
Strong communication and collaboration skills; Ability to navigate ambiguity in a fast-paced, global team environment.
Familiarity with interface protocols (AMBA, AXI, ACE) is desired.
Knowledge of AES, ECC, and RAS features is preferred.
Self-driven, curious, and passionate about logic design and innovation.
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