About the role

  • Junior Verification Engineer on Design Verification team developing high-speed SerDes IP technology. Engaging in constrained-random verification and leveraging AI-assisted tools for engineering workflows.

Responsibilities

  • We're looking for talented, self-motivated engineers to join our Design Verification (DV) team in a junior or mid-level position.
  • We work on some of the most technically challenging silicon in the industry, spanning digital and analog design, DSP pipelines, and firmware-hardware co-verification.
  • Constrained-random and coverage-driven verification of complex high-speed SerDes mixed-signal IP, including advanced verification environment development
  • Validation of DSP datapaths FW/HW joint verification
  • Leveraging AI-assisted tools as a core part of your daily engineering workflow

Requirements

  • Bachelor's degree in EE, CE, or CS — recent graduate with a strong academic record
  • Solid grasp of digital design, computer architecture, and software programming
  • Analytical mindset — you enjoy root-causing problems, not just finding them
  • Ability to thrive in a dynamic, multi-disciplinary environment
  • Hands-on exposure to SystemVerilog/UVM or Python — a significant advantage, but not required

Benefits

  • A collaborative and innovative environment where great ideas come from every level of the team
  • A great place to work — we take the work seriously, and each other's success personally
  • Exposure to the full verification lifecycle — from spec to tape-out sign-off
  • A team culture that embraces modern tooling, including AI-assisted engineering, as a competitive advantage
  • A real growth path from day one

Job title

Junior Verification Engineer

Job type

Experience level

Junior

Salary

Not specified

Degree requirement

Bachelor's Degree

Tech skills

Location requirements

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