About the role

  • Senior Verification Engineer developing and verifying high-speed SerDes mixed-signal IP in a collaborative environment. Collaborate with design, analog, and firmware teams, leveraging advanced verification methodologies.

Responsibilities

  • Own and execute constrained-random and coverage-driven verification of high-speed SerDes mixed-signal IP
  • Develop and maintain advanced SystemVerilog/UVM verification environments
  • Validate DSP datapaths against reference models
  • Contribute to FW/HW joint verification flows
  • Leverage AI-assisted tools as a core part of your daily engineering workflow

Requirements

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or Computer Science
  • 4–7 years of hands-on experience in hardware design verification
  • Solid hands-on SystemVerilog/UVM experience and ability to work independently
  • Strong Python scripting skills for verification automation
  • Deep understanding of digital design and computer architecture
  • Proven ability to take a verification task from plan to closure with minimal guidance
  • Experience collaborating across design, analog, and firmware teams
  • Analytical mindset, you dig until you find the root cause

Benefits

  • A collaborative and innovative environment where great ideas come from every level of the team
  • A great place to work, we take the work seriously, and each other's success personally
  • Exposure to cutting-edge silicon and verification methodology
  • A real growth path with impact beyond your immediate role

Job title

Senior Verification Engineer

Job type

Experience level

Senior

Salary

Not specified

Degree requirement

Bachelor's Degree

Tech skills

Location requirements

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