Physical Design Engineer responsible for implementation of custom IP and SoC designs at Intel. Working on server products and optimizing design parameters in a collaborative engineering environment.
Responsibilities
Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing.
Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.
Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.
Analyzes results and makes recommendations to fix violations for current and future product architecture.
Possesses expertise in various aspects of structural and physical design, including physical clock design, timing closure, coverage analysis, multiple power domain analysis, placing, routing, synthesis, and DFT using industry standard EDA tools.
Optimizes design to improve product level parameters such as power, frequency, and area.
Participates in the development and improvement of physical design methodologies and flow automation.
Requirements
Bachelor's Degree in Electrical or Computer Engineering, Computer Science, or in a STEM related field with 6+ years of experience
Master's Degree in Electrical or Computer Engineering, Computer Science, or in a STEM related field with 5+ years of experience
PhD in Electrical or Computer Engineering, Computer Science, or in a STEM related field with 4+ years of experience
Experience in all aspects of physical design using Synopsys or Cadence tools
Strong background with industry standard tools for synthesis, place and route, and tape out flows
Technical expertise in physical design verification methods such as timing signoff, formal verification, and low power static signoff.
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