Architect RF and mixed-signal microsystems operating across K-band (18–27 GHz), Ka-band (27–40 GHz), and W-band (75–110 GHz) for high-performance, low-latency communication, radar, and sensing applications.
Define and drive RF front-end architectures, including LNAs, PAs, mixers, phase shifters, and T/R modules, optimized for 3.0D integration and advanced packaging flows.
Collaborate with device, packaging, and digital architects to achieve co-optimization of RF, thermal, and mechanical performance within heterogeneous multi-die systems.
Lead EM/circuit co-simulation and system-level modeling using tools such as HFSS, ADS, AWR, or CST to validate and tune design performance across process corners and temperature.
Oversee RF testing, characterization, and calibration at wafer, die, and module levels—developing test plans, de-embedding strategies, and measurement automation for K/W-band hardware.
Engage with foundry, EDA, and metrology partners to define design enablement requirements for next-generation RF packaging (e.g., hybrid bonding, AiP, glass/Si interposers).
Author technical documentation, reference designs, and design guidelines to accelerate ecosystem adoption of TIE’s 3.0D RF microsystems platform.
Other related functions as assigned.
Requirements
M.S. in Electrical Engineering, Applied Physics, or related discipline focused on RF, microwave, or millimeter-wave design.
At least 8 years of hands-on experience designing, simulating, and testing RF/microwave ICs or modules (K-band and above).
Deep expertise in S-parameter characterization, on-wafer measurements, vector network analysis, and de-embedding methodologies.
Proficiency with RF simulation and design tools such as Keysight ADS, Ansys HFSS, Cadence AWR, CST Studio, or equivalent.
Strong understanding of electromagnetic effects in packaging—signal integrity, coupling, and loss across interposers and redistribution layers.
Proven track record in RF testing automation, data analysis, and test correlation between EM models and measured results.
Ability to work cross-functionally with device, packaging, EDA, and system teams in a fast-moving R&D environment.
Benefits
Competitive health benefits (employee premiums covered at 100%, family premiums at 50%)
Voluntary Vision, Dental, Life, and Disability insurance options
Generous paid vacation, sick time, and holidays
Teachers Retirement System of Texas, a defined benefit retirement plan, with 8.25% employer matching funds
Additional Voluntary Retirement Programs: Tax Sheltered Annuity 403(b) and a Deferred Compensation program 457(b)
Flexible spending account options for medical and childcare expenses
Robust free training access through LinkedIn Learning plus professional conference opportunities
Tuition assistance
Expansive employee discount program including athletic tickets
Free access to UT Austin's libraries and museums with staff ID card
Free rides on all UT Shuttle and Austin CapMetro buses with staff ID card
Architect maintaining architectural quality and compliance with client’s design vision for Bureau Veritas. Reviewing drawings and coordinating with teams for project success in Amaravathi, India.
CPU Micro - Architect responsible for designing high - performance architectures for mobile and computing devices at Samsung. Join the team to innovate in semiconductor technology and solutions.
Success Architect providing expertise for Salesforce products and assisting clients in maximizing business value using Salesforce. Responsible for overcoming technical and business challenges using best practices and expertise.
CMBU Architecture Director for DDR Memory at Micron Technology leading a high - performing engineering team. Responsible for defining DDR solutions focused on next generation datacenter systems.
CMBU Systems Architecture Engineer at Micron Technology defining optimized memory and storage solutions for AI training. Collaborating with industry partners and mentoring junior engineers.
CMBU Product Architecture Engineer defining optimized DRAM solutions for AI at Micron Technology. Collaborating with cross - functional teams and stakeholders in the semiconductor industry.
Senior Cloud Architect at ControlExpert shaping international cloud solutions with AWS expertise. Leading architecture analyses and collaborating closely with DevOps and SecOps teams.
Architecte SAP S/4HANA contribuant à la définition de modèles ERP pour la transformation digitale. Recherche un consultant en systèmes SAP pour un projet en phase de Discovery.
Domain Architect for Data at Airbus, designing architecture for digital solutions and collaborating across teams. Focusing on data - centric initiatives and complex IT products.
Design Engagement Lead working with A&D clients to solve problems through creative product design. Leading opportunities validation and telling the story of the Custom Studio.