Hybrid Lead ASIC-FPGA Verification Engineer

at Boeing

• Job title: Lead ASIC-FPGA Verification Engineer
• Job type: Full Time
• Experience level: Senior
• Salary: Not specified
• Degree requirement: Bachelor's Degree
• Location requirements: Hybrid, Bangalore, India

About the role

• Lead ASIC-FPGA Verification Engineer at Boeing India working on commercial and defense electronics. Responsibilities include verification for ASIC and FPGA products and team collaboration.

Responsibilities

• Use high-level architectural documentation along with algorithm description and implement functions for test bench architecture and test plan using UVM for IP, Subsystem and System level verification
• Develop reusable testbench components like scoreboards, checkers, reference models along with UVC using SV and UVM
• Own quality of deliverables for verification across multiple milestones for FPGA/ASIC life cycle
• Architect Reusable Verification components, which can be used across FPGA/ASIC life cycle
• Lead, drive and collaborate technical reviews with Validation, Design and System Architecture cross functional teams
• Support Architecture exploration at system level using System C or TLM models using SV-UVM Verification Domain expert for PCIe and Ethernet protocols
• Identifies, tracks and status technical performance measures to measure progress and ensure compliance with verification requirements
• Develop Junior engineers, solve simple to complex technical problems in verification

Requirements

• Bachelor degree in Engineering, Engineering Technology, Computer Science, Data Science, Mathematics, Physics, Chemistry, or non-US equivalent qualifications
• 13 to 17 years of experience in Digital Functional verification for both ASIC and FPGA at IP, Subsystem and System level as a Lead or Verification Architect
• 8+ years of experience in leading verification Activities for Multiple ASIC and FPGA product Tape outs
• 7+ years of experience in Developing and mentoring Verification engineers
• 5+ years of Hands-on domain experience on PCIe (Transaction layer) and Ethernet (Mac Layer)
• 5+ years of experience doing UVM based Testbench Architecture for PCIe and Ethernet across IP/Subsystem and system level for multiple projects in ASIC and FPGA

Benefits

• Variable arrangements depending upon business and customer needs
• Professional pursuits that offer greater flexibility
• Collaboration, frequent team engagements, and face-to-face meetings