Hybrid Staff Design Verification Engineer, Memory Controller

Posted 2 weeks ago

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About the role

  • contribute to the functional verification of LPDDR memory controllers
  • architect and build re-usable testbenches right from scratch
  • propose and drive best practices/methodologies/automation that can improve productivity
  • own key features and timely execution of tasks as per milestones
  • create test plans as per spec and present to various stakeholders
  • work with designers to resolve any spec issues
  • collaborate with designers to verify the correctness of a design feature and resolve fails
  • develop assertions, checkers, covergroups, Systemverilog constraints
  • analyze and debug, root causing functional fails from regressions
  • perform coverage gap analysis, identifying coverage exclusions and improving stimulus
  • integrate memory models (VIP) from vendors into TB and bringup
  • develop fake PHY models and bringup
  • verify DRAM interface training, Link ECC/EDC, Command/WR/RD paths, Schedulers, DVFS, Power Down, Self-Refresh
  • work with SoC team to debug functional fails during IP bringup and feature execution
  • collaborate with Performance Verification teams to help with co-sim TB bringup
  • help with Silicon bringup and root causing fails
  • mentor junior team members, work independently, and be a team player

Requirements

  • 10+ years of experience with a Bachelor’s degree in Computer Science/Computer Engineering/relevant technical field, or 8+ years of experience with a Master’s degree, or 6+ years of experience with a PhD
  • 8+ years industry experience in a design verification role
  • Expert hands-on coding skills in Testbench, Stimulus, checker development & coverage closure
  • Experience with System Verilog, UVM or equivalent
  • Experience with LPDDR5/5X/6 memory model VIPs
  • Experience with DDR/LPDDR/HBM protocols
  • Experience with Git version control, Unix/Perl/Python scripting
  • Combined experience with coherent interconnect, caches, and LPDDR memory controllers is highly preferred
  • Formal verification skills will be a plus
  • Good written and verbal communication skills

Benefits

  • medical
  • dental
  • vision
  • life insurance
  • 401(k)
  • free onsite lunch
  • employee purchase program
  • tuition assistance (after 6 months)
  • paid time off
  • student loan program
  • wellness incentives
  • MBO bonus compensation based on company, division, and individual performance
  • potential participation in long term incentive plan
  • relocation assistance

Job title

Staff Design Verification Engineer, Memory Controller

Job type

Experience level

Lead

Salary

$151,000 - $239,200 per year

Degree requirement

Bachelor's Degree

Tech skills

Location requirements

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