Contribute to defining and leading the formal verification strategy for our systems.
Work closely with system architects and design team to establish formal verification environment and setting.
Guide the use of formal verification so that correct formal techniques are used appropriately to improve efficiency of IP and SoC level verification.
Contribute to define Formal Verification Methodologies.
Produce IP level, subsystem level and chip level test plans based on Design documents and interaction with design and architecture teams.
Write and debug System Verilog assertions.
Analyze coverage data and working with Design teams to address coverage holes.
Contribute to developing framework for running regressions and debugging regression failures.
Support integration of design in higher-level subsystem including test planning, test vector delivery, and debug of test vectors at the integration level.
Scripting/Automation skills for improving workflows along with the usage of most advanced AI techniques.
Participate in project reviews.
Provide supervision/guidance to other team members.
Requirements
Master’s degree in relevant field
Min 5 years of experience in relevant field of Formal Verification
A deep understanding of formal verification, including applications, verification of algorithms, protocols, and application of formal verification at SoC level
Made significant contributions in the use of formal verification and be able to guide formal verification development into new areas
Formal tools, System Verilog, SV Assertions and Assumptions, Scripting skills
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