Digital Verification Engineer verifying SystemVerilog IP for a wireless SoC with simulation methodologies. Collaborate with design and architecture teams to drive verification strategy and practices.
Responsibilities
Develop and maintain simulation-based verification environments for SystemVerilog RTL (UVM and/or cocotb-based flows).
Create scalable testbenches, drivers/monitors, scoreboards, reference models, and coverage (functional/code) to validate IP and SoC behavior.
Build and execute constrained-random and directed tests; debug failures across RTL, testbench, and tool flows.
Define verification plans, coverage goals, and bring-up strategies in collaboration with design and architecture.
Drive regressions and continuous integration for verification, including test triage, automation, and reporting.
Contribute to verification best practices (assertions, checkers, reuse, documentation) across the Core Platform.
Requirements
BS/MS/PhD in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience.
3+ years of digital verification experience (or equivalent), including verification of non-trivial IP blocks and/or SoCs.
Strong SystemVerilog skills and comfort reading/debugging RTL.
Hands-on experience with at least one simulation-based verification methodology: UVM (SystemVerilog class-based verification), and/or cocotb (Python-based verification) or similar framework, with modern verification practices.
Proficiency debugging simulation issues (waveforms, logs, assertions) and working with common EDA simulators.
Experience verifying complex systems (multi-clock domains, bus fabrics, interrupts, DMA, low-power states, or similar SoC features).
Solid scripting ability (Python preferred; bash/tcl a plus) for test automation and tooling.
Benefits
Waveworks is committed to a friendly and welcoming working environment.
Waveworks does not discriminate based on race, gender, age, religious affiliation, or any other legally protected status.
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