Performance Engineer optimizing GPU training for foundation models in Heidelberg. Join a team focused on improving efficiency and effectiveness in AI training systems.
About the role
- Verification Engineer at NVIDIA creating UVM test benches and methodologies for verifying automotive chips. Collaborating with cross-functional teams on next generation automotive systems and technologies in India.
Responsibilities
- Be responsible for creation of "state of the art" UVM based verification test benches and methodologies to verify complex IP's and Sub-systems.
- Work on System level verification using C/C++.
- Architect the testbenches and craft verification environment using UVM methodology.
- Define test plans, tests and verification infrastructure for modules, clusters and system.
- Build efficient and reusable bus functional models, monitors, checkers and scoreboards.
- Implement functional coverage and own verification closure.
- Work with architects, designers, FPGA and post-silicon teams to ensure that your unit is robust.
Requirements
- BTech/MTech with 3+ years of experience in verification closure of complex Unit, Sub-system or SOC level verification.
- Experience in CPU verification, Memory controller verification, Interconnect verification, High Speed IO verification (UFS/PCIE/XUSB), 10G/1G Ethernet MAC and Switch, Bus protocols (AXI/APB), System functions like Safety, Security, Virtualization and sensor processing
- Experience in the latest verification methodologies like UVM/VMM
- Exposure to industry standard verification tools for simulation and debug
- Exposure to Formal verification would be excellent
- Good debugging and analytical skills.
Benefits
- Comprehensive benefits package
Job title
Job type
Experience level
Salary
Not specified
Degree requirement
Location requirements
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