Onsite HBM Memory Subsystem Architect – MTS/SMTS/DMTS

Posted 9 hours ago

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About the role

  • Memory Subsystem Architect focusing on innovative HBM product solutions for AI/ML workloads. Collaborating with cross-functional teams to drive architectural planning and performance analysis.

Responsibilities

  • Develop innovative memory subsystem frameworks for HBM solutions supporting AI/ML workloads
  • Define Memory and RAS architecture requirements and drive architectural planning for next generation memory subsystems
  • Collaborate with internal and external partners to develop novel architectures and detailed IP requirements
  • Lead engagement with IP vendors, including evaluation and selection of interface and functional IP
  • Analyze benchmarks, workloads, and simulations to identify opportunities for performance, efficiency, and architectural innovation

Requirements

  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
  • Minimum of 12 years of experience in memory subsystem architecture and design
  • Deep understanding of memory controller design and memory types (DDR, LPDDR, GDDR, HBM)
  • Experience with PHY design and understanding of signal integrity issues
  • Familiarity with industry-standard bus protocols such as AXI, AMBA, AHB, DFI, etc.

Benefits

  • Choice of medical, dental and vision plans
  • Income protection programs
  • Paid family leave
  • Robust paid time-off program
  • Paid holidays

Job title

HBM Memory Subsystem Architect – MTS/SMTS/DMTS

Job type

Experience level

SeniorLead

Salary

$177,000 - $387,000 per year

Degree requirement

Bachelor's Degree

Location requirements

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