Hybrid ASIC Design Verification Engineer – All Levels

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About the role

  • Design Verification Engineer verifying circuitry for state-of-the-art AI SoCs at Marvell. Develop verification architecture and ensure test plans meet coverage goals with the R&D team in San Diego.

Responsibilities

  • develop the architecture for a functional verification environment, including reference models and bus-functional monitors and drivers
  • contribute to the methodology behind such development
  • writing a verification test plan using random techniques and coverage analysis
  • working with designers to ensure it is complete
  • developing tests and tuning the environment to achieve coverage goals
  • debugging failures and working with designers to resolve issues
  • verifying boot code
  • architecting, developing, and maintaining tools to streamline the design of state-of-the-art multi-core SoCs
  • transforming the requirements from the engineering teams into software tools that are both easy to use and scalable within a highly parallel compute environment
  • unit and regression testing of software tools

Requirements

  • BS Computer Engineering, Electrical Engineering, or Computer Science with 4-10+ years of verification experience or MS/PhD with 2-10+ years experience
  • Experience with SystemVerilog, UVM
  • Experience with writing a detailed test plan and building a sophisticated, directed, random-verification environment
  • Experience with scripting language such as Python or Perl and EDA Verification tools
  • Experience with Object-Oriented Design and implementation
  • Good understanding of Linux O.S.
  • Good programming skills desired, especially C++ and ARM assembly
  • Understanding of networking protocols, a plus
  • Diligent, detail-oriented, and willing to take initiative and handle assignments with minimal supervision
  • Requires the ability to accept and work with differing opinions
  • Cannot be a close-minded developer
  • Must be able to learn on the fly and work in a fast-paced environment

Benefits

  • employee stock purchase plan with a 2-year look back
  • family support programs to help balance work and home life
  • robust mental health resources to prioritize emotional well-being
  • recognition and service awards to celebrate contributions and milestones

Job title

ASIC Design Verification Engineer – All Levels

Job type

Experience level

Mid levelSenior

Salary

$160,400 - $237,320 per year

Degree requirement

Bachelor's Degree

Location requirements

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