Analyst Programmer developing applications to enhance call center operations and analytics. Assisting in diverse program implementation and providing user support for functionalities.
About the role
- Intern role focusing on FPGA/ASIC design and verification at Teradyne. Collaborating with teams on design reviews and project goals.
Responsibilities
- Interns will work as part of a team.
- Roles and responsibilities touch on FPGA/ASIC design implementation, specification analysis, and design verification.
- Participate in design reviews, failure analysis, and more broadly in achieving project goals.
Requirements
- Qualified applicants must be currently enrolled in a BS or MS degree program
- Qualified majors are EE or CE
- Must be currently enrolled in JR or SR level in BS degree program with 3.2 GPA or greater - OR Currently enrolled MS level students with minimum GPA of 3.2 or greater.
- Qualified applicants will have course work focused on FPGA/ASIC Design with verilog or other HDL, or course work focused on FPGA/ASIC Verification with verilog or other HDL
- Must be available to work on site at the North Reading, Massachusetts office as needed.
- Must be available during the summer break (May - September) based on school schedule
- Excellent written and verbal communication skills.
- Ability to work in a fast paced and challenging environment
- Self-starter. Ability to recognize gaps in his or her own knowledge and seek out answers.
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