Construction Engineer creating 3D models and drawings for power plants, optimizing existing designs, collaborating with teams and suppliers.
About the role
- SOC Design Engineer developing logic design and RTL for AI System on Chips at Intel. Focused on integration, architecture definition, and design qualifications on semiconductor innovations.
Responsibilities
- Develops the logic design, register transfer level (RTL) coding, simulation, and integrates the compute IP block for AI SoCs at the full-chip level.
- Participates in the definition of architecture and microarchitecture features of the block being designed.
- Qualifies the design through static design quality checks like lint, CDC, RDC, etc.
- Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, timing goals, and design integrity for physical implementation.
- Reviews the verification plan and implementation to ensure design features are verified correctly across verification hierarchies.
- Drives unit level verification, resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
Requirements
- 8+ years of experience in/with Verilog/SystemVerilog
- Microarchitecture
- Modern design techniques and energy-efficient/low power logic design and power analysis
- Computer Architecture
- 5+ years of experience with SoC design and integration
- experience in multiple tape-outs reaching production with first pass silicon
Benefits
- competitive pay
- stock bonuses
- benefit programs which include health
- retirement
- vacation
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