Surface Designer creating custom artwork at Phillip Jeffries for luxury wallcoverings. Collaborating on designs and preparing files for production with a focus on creativity and detail.
About the role
- Verification Engineer for Altera designing robust verification environments and validating software abstractions for FPGAs. Collaborating with design engineers to enhance verification strategies and uncover bugs.
Responsibilities
- Collaborate with architects and design engineers to understand IP specifications and define comprehensive verification strategies and detailed test plans.
- Develop robust, reusable, and constrained-random verification environments using SystemVerilog and UVM (Universal Verification Methodology).
- Create and implement directed and random test cases and test sequences to exercise design functionality and uncover potential bugs.
- Develop verification components, including drivers, monitors, scoreboards, and checkers.
- Utilize SystemVerilog Assertions (SVA) and formal verification methods to enhance bug detection and verify complex properties.
- Execute simulation regressions, debug test failures, analyze root causes, and work with designers to implement corrective measures.
- Define and track functional and code coverage metrics to ensure verification completeness and drive coverage closure.
- Develop automation scripts and infrastructure using languages like Python or Perl to improve verification efficiency and flows.
- Participate in technical reviews of specifications, design documents, and test plans, providing valuable input and feedback.
Requirements
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
- 9+ years of experience in ASIC or FPGA design verification.
- Expertise in Hardware Description Languages (HDL) like Verilog or VHDL and Hardware Verification Languages (HVL) such as SystemVerilog.
- Strong hands-on experience in developing UVM-based testbenches and verification components.
- Proficiency in modern verification methodologies, including coverage-driven verification (CDV) and assertion-based verification (ABV).
- Familiarity with industry-standard protocols such as AMBA (AXI, ACE, CHI, APB), PCIe, or Ethernet is a plus.
- Experience with simulation and debug tools.
- Strong scripting skills in Python, Perl, or Tcl for automation and data analysis.
- Excellent analytical, problem-solving, and debugging skills.
- Strong communication skills and the ability to work effectively in a collaborative, cross-functional team environment.
Benefits
- Health insurance
- Retirement plans
- Professional development opportunities
Job title
Job type
Experience level
Salary
Not specified
Degree requirement
Tech skills
Location requirements
UN
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