Senior Design Engineer developing cutting-edge AI SoC products for various applications. Focused on logic design, RTL coding, and microarchitecture in a collaborative environment.
Responsibilities
develop logic design, register transfer level (RTL) coding, and simulation for SoC designs while integrating IP blocks
participate in defining architecture and microarchitecture features of the blocks being designed
perform quality checks across various logic design aspects ranging from RTL to timing/power convergence
apply various strategies, tools, and methods to write RTL and optimize logic
ensure design integrity for physical implementation
work closely with verification teams, review verification plans and implementation
resolve and implement corrective measures for failing RTL tests
follow secure development practices to address security threat models and objectives
collaborate closely with physical design teams for synthesis, timing closure, and formal equivalence checks
mentor junior engineers and contribute to best practices for design methodology and quality
Requirements
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or Computer Science
7+ years of experience in RTL design and implementation for ASIC/SoC development
Proven ability to solve complex design challenges such as clock domain crossings, power optimization, and timing closure
Hands-on experience with SoC system integration and multicore CPU subsystem design
Strong knowledge of standard bus protocols (AXI, AHB, etc.) and embedded processor architectures
Expertise in high-speed and low-power design techniques
Proficiency in scripting (Python, TCL, etc.) for automation and design flow optimization
Familiarity with industry standard EDA tools, including simulators (VCS, Questa, Xcelium), lint tools (Spyglass), and FPGA prototyping tools (Xilinx Vivado, Altera Quartus II)
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