Senior Mechanical Engineer designing and analyzing electro - opto - mechanical systems at ZEISS. Involves project management, system analysis, and cross - functional collaboration for product development.
About the role
- Lead the layout design for high-complexity AI accelerator PCBAs at d-Matrix. Oversee design methodology and automation in a hybrid work environment.
Responsibilities
- Lead the layout for high-complexity AI accelerator cards (PCIe form factors) and massive system baseboards.
- Architect and manage the Constraint Manager (CM) hierarchy within Cadence Allegro.
- Drive productivity by developing or implementing automation scripts (SKILL, Python, or TCL).
- Execute layout for ultra-high-speed interfaces, including PCIe Gen5/6, CXL, and custom die-to-die (D2D) interconnects.
- Work with Power Engineers to implement complex PDN strategies.
- Drive the definition of PCB stack-ups with advanced low-loss materials.
- Act as the primary interface with PCB fabricators and CMs for DFM, DFT, and DFA requirements.
Requirements
- BS in Electrical/Electronic Engineering or equivalent practical experience.
- 12+ years of experience in high-speed, high-density PCB layout for servers, networking, or AI accelerators.
- Expert-level proficiency in Cadence Allegro Constraint Manager, including the setup of complex T-junctions, differential pair phase-tuning, and Z-axis delay matching.
- Proven ability to write and deploy SKILL scripts or utilize Allegro’s API to automate design audits and layout routines.
- Deep understanding of high-speed routing (back-drilling, via-in-pad, and skip-vias).
Benefits
- Medical/Dental/Vision/401k
- Diverse package of benefits centered around the wellbeing of our employees and their loved ones
- Incentive opportunities that reward employees based on individual and company performance
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