Intermediate Water Resources Engineer focusing on mining in a multidisciplinary team environment. Lead studies, assessments, and investigations with a commitment to health and safety standards.
About the role
- SoC Verification Engineer focusing on RTL verification for SoC designs at Fraunhofer Institute. Collaborating with teams to build reusable verification environments utilizing RISC-V architecture.
Responsibilities
- Understanding the nuances of RISC-V architectures
- Translating design specifications into comprehensive verification plans
- Developing and maintaining reusable test environments
- Creating and analyzing coverage models
- Debugging test failures and managing defect tracking
- Conducting verification reviews for quality assurance
- Preparing, executing, and evaluating regression tests
Requirements
- Completed university degree in (electrical) engineering, IT/computer science, or a related field
- Strong understanding of digital logic design and RISC-V architecture
- Proven experience with SystemVerilog and UVM-based verification environments
- Very good English and good German language skills
- Proactive and independent mindset
- Desirable: Familiarity with C/C++ programming, assembly, and object-oriented languages such as Python
- Knowledge of industry-standard interfaces and bus protocols (e.g., AXI)
- Experience with IP verification methodologies, integration verification specifically for RISC-V, and embedded CPU verification
- Interest in low-power verification techniques and formal verification tools (e.g., JasperGold)
Benefits
- Professional development: high-quality work equipment and regular training
- Flexible working hours: a range of options to help balance personal and professional responsibilities
- Institute culture: appreciative and supportive work atmosphere within an international team
Job title
Job type
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