Onsite DMTS NOC Cache Coherency Architect

Posted 1 hour ago

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About the role

  • NOC and Cache Coherency Architect leading design efforts on NOC, Coherency Manager, and Cache Controller components at GlobalFoundries. Collaborating with CPU core architects and teams for high-quality processor designs.

Responsibilities

  • Lead and drive architectural specification and design activities for Coherency Manager and Cache Controller IP to closure.
  • Collaborate closely with design teams and architects to thoroughly understand and interpret microarchitectural and functional specifications.
  • Automate and optimize verification flows and regression environments using scripting languages like Python, Perl, TCL, or Shell.
  • Mentor design engineers, providing technical guidance and leadership within the verification team.

Requirements

  • Master’s degree or higher in Electronics/Electrical/Computer Engineering.
  • 15+ years of relevant verification experience, specifically in CPU or complex SoC verification.
  • Proven expertise in Multicore and Multicluster Coherency, Cache Controllers, or similar blocks.
  • Proficiency in SystemVerilog, Verilog, C/C++, and Assembly.
  • Solid understanding of interconnect and coherency protocols such as AXI, ACE, OCP, CHI.
  • Strong scripting skills in Python, Perl, TCL, or Shell.
  • Experience with CPU architectures, particularly RISC-V, ARM, or MIPS.

Benefits

  • Opportunity to be part of a dynamic team creating industry-leading RISC-V processors.
  • Autonomy with extensive support from industry experts.
  • Opportunities for significant career growth and technical advancement.
  • Competitive compensation and comprehensive benefits package.

Job title

DMTS NOC Cache Coherency Architect

Job type

Experience level

SeniorLead

Salary

$166,500 - $290,000 per year

Degree requirement

Postgraduate Degree

Location requirements

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