Mechanical Engineer working on mechanical service projects from feasibility to construction stages. Ensuring compliance with industry regulations and building services standards in a hybrid work environment.
About the role
- Participate in IP level architectural definition including micro-architecture definition
- Perform RTL design using Verilog HDL, with an emphasis on performance and area
- Implement multi-power and low-power designs
- Analyze and resolve Lint and Clock/Reset Domain crossing issues in the design
- Collaborate with verification team on test plan development, debugging, and coverage closure
- Collaborate with physical design team on constraint generation, timing closure analysis, formal verification, low power checks using UPF/CPF flows and ECO implementation
- Support system level validation efforts on FPGA/emulation
- Support silicon bring-up and debug efforts
Requirements
- BS+12 Years of relevant industry experience
- Advanced degree preferred
- Must have strong Logic Design, RTL coding (Verilog HDL) and debugging skills
- Must have an understanding of low power design and validation techniques including UPF/CPF
- Must be familiar with design constraint generation, logic synthesis, timing closure analysis and Clock/Reset domain crossing checks
- Must be able to assist in silicon and FPGA debug and bring-up
- Experience with ARM CPUs, Memory controllers, I2C, SPI, UART, APB, AHB, AXI
- Experience with Digital Signal Processing designs, usage of Matlab and Simulink, Scripting languages (Python, perl/tcl), Mixed signal design
Benefits
- Medical, dental and vision plans
- 401(K) participation including company matching
- Employee Stock Purchase Program (ESPP)
- Employee Assistance Program (EAP)
- Company paid holidays
- Paid sick leave and vacation time
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