NV
Senior ASIC Design Engineer in NVIDIA's Switch Silicon team developing groundbreaking high - speed communication devices. Responsible for RTL implementation and collaboration with cross - functional engineering teams.
About the role
- A role in physical design for NVIDIA GPU and Mobile chips.
- Participate in various aspects of physical design, including full chip floorplanning, power/clock distribution, timing optimization, place & route, timing closure, power/signal integrity analysis, and physical verification.
- Troubleshoot a wide variety of design and flow complicated issues, and apply proactive intervention.
- Collaborate with RTL, DFT and Circuit designers to ensure high quality of design implementation.
Requirements
- BS in Engineering or Science or equivalent experience.
- Power user of EDA tools from Synopsys (ICC2/FC/PT/STAR-RC), Cadence (EDI/Innovus/Voltus).
- Experience in Clock/Power Distribution, P&R, Timing closure, RC Extraction, and verification on advanced technology nodes.
- 2+ years of experience in above areas.
- MS in Engineering or Science is a plus.
- Knowledge in FinFET technology, circuit design, and package design.
- Experience in physical verification tools from Synopsys (ICV) or Mentor (Calibre).
- Proficiency in Perl, Python, TCL and Makefile scripts.
Job title
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Salary
Not specified
Degree requirement
Tech skills
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