Senior Director managing wealth management advisors in Coralville, IA. Driving client relationship growth and strategic business initiatives for TIAA.
About the role
- Director of Silicon Logical Design leading and scaling digital design organization for AI accelerators. Responsible for architectural realization and integration from specification through tape-out.
Responsibilities
- Lead and grow the silicon logical (digital) design team, including RTL, integration, and design methodology
- Drive the translation of system and micro-architecture specifications into high-quality RTL implementations
- Own the end-to-end logical design execution for one or more SoCs, from concept through tape-out
- Partner closely with architecture, verification, physical design, DFT, software, and product teams to ensure robust and scalable designs
- Define and enforce best practices for RTL quality, coding standards, reuse, and design reviews
- Oversee block-level and top-level integration, ensuring performance, power, area, and schedule targets are met
- Support bring-up, debug, and silicon validation activities, including root-cause analysis of silicon issues
- Contribute to long-term technology and roadmap planning, including IP strategy and future architecture directions
- Mentor and develop engineers, fostering a culture of technical excellence, ownership, and collaboration
Requirements
- Extensive experience in digital / logical design for complex SoCs, with multiple successful tape-outs
- Proven ability to lead and grow high-performing silicon design teams
- Strong expertise in RTL and micro-architecture development (SystemVerilog / Verilog)
- Experience with large-scale SoC integration, including CPUs, accelerators, memory subsystems, and interconnects
- Solid understanding of performance, power, and area trade-offs in advanced process nodes
- Experience working closely with verification and physical design teams to achieve functional and timing closure
- Strong communication skills and the ability to operate at both strategic and hands-on technical levels
- **+ Preferred:**
- Experience with AI/ML accelerators, GPUs, NPUs, or high-performance compute architectures
- Familiarity with industry-standard interconnects (e.g., AXI, NoC architectures)
- Knowledge of low-power design techniques and multi-clock / multi-voltage systems
- Experience with silicon bring-up, post-silicon debug, and root-cause analysis
- Experience working in a startup or fast-scaling environment
Benefits
- Attractive compensation package
- Pension plan
- Extensive employee insurances
- Option to get company shares
- Flexible working arrangements
- Open culture that supports creativity and continual innovation
Job title
Job type
Experience level
Salary
Not specified
Degree requirement
Location requirements
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