Own the product from design through high volume production ramp
Identify, drive test cost reduction, improve both CP and FT yield
Enhance CP program to minimize high FT yield fallout bins
Requirements
Strong academic and technical background in electrical engineering. At minimum, a Bachelor’s in EE is required, and a Master’s is preferred.
8-year experience releasing complex SoC/silicon products to high volume manufacturing.
Working knowledge of high-speed protocols like PCIe, LPDDRx, HBM, etc.
Hands-on experience with high-speed SoC test program/hardware development on Advantest 93k test platform.
Collaboration with design DFT team to define test strategy, create and own test plan.
Familiar with high-speed and high power load board design techniques
Proven track record of implementing ATE patterns to optimize tester resources and minimize ATE test time while maintaining product quality.
Strong knowledge and development of DFT techniques implemented in silicon that provide maximum defect and parametric device coverage – AC/DC SCAN, MBIST, DBIst, DSerDes, DDR, D2D, DIMC and other functional tests.
Strong knowledge of lot genealogy from 2DiD bar code down to ECID in eFuse for device serial number, chiplet Id and die information.
Expertise in production test of high speed SerDes operating at 16Gbps and higher.
Skilled in ATE programming, silicon/ATE bring-up, bench-ATE correlation and debug.
Experience with lab equipment including protocol analyzers and oscilloscopes.
Experience with data conversion between STDF file format into csv file format using scripts including extracting ECID reside with eFuse block.
Proficiency in modern programming languages such as C/C++, Python.
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