contribute to the functional verification of System IP, including coherent interconnect, caches, and dynamic memory controllers
drive hands-on project execution and provide expertise in design verification
serve as the technical expert for verification know-how and micro-architecture
design and build reusable testbenches from scratch
identify and propose solutions to improve existing verification flows
architect next gen verification test benches and flows to boost productivity
develop and implement best practices to enhance productivity
own key features and execute tasks to meet milestones
create test plans, challenge specs, and review test plans/code
collaborate with designers to resolve spec issues and verify design correctness
develop verification environments, stimulus, and tests
debug and root cause functional fails from regressions
analyze code and functional coverage results, performing gap analysis
identify coverage exclusions and improve stimulus
collaborate with SoC, Physical Design, and Performance Verification teams to debug and resolve issues
help with Silicon debug issues
provide mentorship to junior team members
Requirements
20+ years of experience with a Bachelor’s degree in Computer Science/Computer Engineering/relevant technical field, or 18+ years of experience with a Master’s degree, or 16+ years of experience with a PhD
15+ years of industry experience in design verification
Expert-level SystemVerilog and UVM coding skills
Knowledge of ARM protocols (CHI, AXI, ACElite, APB)
Experience with Git version control and Unix/Perl scripting
Must have Coherent interconnect verification experience
Familiarity with both coherent interconnect and LPDDR memory controllers (ideal)
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