Contact Us

Hybrid Layout Engineer

at Factorial
Visit Factorial websiteVisit Factorial LinkedIn

Posted last month

Apply now

About the role

  • Develop and own the top-level floorplan for complex SoCs, from early-stage planning to final implementation handoff.
  • Utilize Cadence Virtuoso to perform block placement, macro integration (SRAMs, analog IP), and chip-level assembly.
  • Manage the third-party IPs, taking care of the retrieval and storage.
  • Design, implement, and analyze the chip's power delivery network (PDN) to ensure electrical and performance robustness.
  • Work closely with analog and digital design teams to ensure the seamless integration of custom blocks and IPs at the chip level.
  • Perform early-stage routing feasibility studies, I/O ring planning, and critical pin assignments.
  • Run top-level physical verification (DRC, LVS, ERC) using industry-standard tools to ensure the floorplan is clean and manufacturable.
  • Develop and maintain WSP for custom layout integration.
  • Develop and maintain automation scripts (using SKILL, Tcl, or Python) to improve floorplanning efficiency and flow predictability.

Requirements

  • Technical diploma or Relevant experience in the field.
  • 5+ years of direct experience in physical layout or physical design, with a strong focus on chip-level floorplanning.
  • Expert-level proficiency with Cadence Virtuoso for custom layout and top-level chip assembly.
  • Practical experience with physical verification tools (e.g., Siemens/Mentor Calibre).
  • A solid understanding of power grid design principles and IR drop analysis.
  • Strong scripting skills in SKILL, Tcl, or Python.
  • Meticulous attention to detail and excellent problem-solving abilities.
  • Experience with advanced technology nodes (e.g., 7nm/5nm FinFET) preferred.
  • Familiarity with mixed-signal or custom-digital design flows preferred.
  • Knowledge of low-power design methodologies (UPF) preferred.
  • Familiarity with the open-source hardware ecosystem (e.g., RISC-V) preferred.

Benefits

  • A highly competitive salary and benefits package.
  • A flexible, collaborative, and results-oriented work environment.
  • The opportunity to work on revolutionary projects with a global impact.
  • A dedicated budget for training and professional growth.
  • The chance to actively contribute to a fast-growing company.

Job title

Layout Engineer

Job type

Full Time

Experience level

Mid levelSenior

Salary

Not specified

Degree requirement

Professional Certificate

Tech skills

AssemblyPython

Location requirements

HybridRomaItaly

Report this job

See something inaccurate? Let us know and we'll update the listing.

Report job

Similar roles

Browse all Software Engineer jobs
Red HatEngineering Manager

Software Engineering Manager leading a global team at Red Hat, delivering features for the OpenShift Service on AWS. Driving technical discussions and championing AI adoption within engineering workflows.

Hybrid Role
United StatesSoftware Engineer
$148,540 - $245,050 per year
CIEE RioEstágio em Engenharia

Internship in Engineering roles at TBG Campinas for students with availability for 2 years. Engage with activities in the engineering field while gaining practical experience.

Hybrid Role
CampinasBrazilSoftware Engineer
Digitale Leute SchoolJunior Software Entwickler

AI Software Engineer role at Digitale Leute School focusing on AI - driven software development. Engage with product management methods and participate in groundbreaking training programs.

Hybrid Role
HamburgGermanySoftware Engineer