Hybrid Hardware Engineering Internship

at Riverlane

• Job title: Hardware Engineering Internship
• Job type: Internship
• Experience level: Entry level
• Salary: £30,000 - £35,000 per year
• Degree requirement: Bachelor's Degree
• Tech skills: Python
• Location requirements: Hybrid, Cambridge, United Kingdom

About the role

• Engineering Intern responsible for optimizing the local clustering decoder for quantum error correction at Riverlane. Collaborating with engineers and contributing to design decisions in quantum computing.

Responsibilities

• Collaborate with experienced hardware and software engineers to explore architectural optimisations
• Enhance the decoder’s architecture to improve flexibility and processing speed
• Contribute to design decisions involving space/time trade-offs for performance

Requirements

• Proficiency in Python
• Solid understanding of low-level computer architecture
• Willingness to learn about FPGA development, quantum computing, and quantum error correction
• Familiarity with quantum computing or quantum error correction (even better)
• Understanding of optimisation concepts
• Exposure to networking principles
• Experience with RTL (Register Transfer Level) development for FPGA/ASIC

Benefits

• Competitive stipend
• Payment for expenses incurred in role (e.g. travel)
• Diverse work environment
• Regular learning events
• Complimentary snacks and refreshments
• Social and cultural events