Assist design unit owner in Register Transfer Level RTL model functional validation
Use CAD tool extensively to simulate logic behavior and circuit performance and direction of physical design for next generation, deep sub-micron embedded circuit solutions
Verify the circuit behavior against the original simulation model and first silicon
Define VLSI Structural Design methodology and developing design flows
Implement structural physical designs, such as synthesis, floor planning, timing budgeting and closure, place and route
Develop Analog IP on next generation deep submicron process for the Intel's SOC
Responsible for Integration of Third party IPs.
Requirements
Bachelor of Engineering degree or a Master of Science degree in Electronic, Electrical or Computer Engineering
Familiarity with Very Large Scale Integration VLSI Complementary Metal-Oxide Semiconductor CMOS logic circuit design
Well versed in UNIX, C programming and relevant Computer Aided Design CAD tools.
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