Position in design, modeling, and verification of custom analog designs for high-speed serdes transceivers in advanced technology nodes
Design and verification of analog circuits, following prescribed design and documentation flows, to meet architecture specifications
If necessary, support and interact with customers on requirements, design specifications, performance results and product delivery
Support analog IP and chip level integration
Collaborate with architects, technical leads, analog and digital design, layout, integration, verification, silicon validation and quality teams as needed
Requirements
Master's or Ph.D. degree in Electronics or other relevant fields
Minimum 5 years of experience in analog design and layout of key circuits in multi-gigabit serial data-link transceivers or RF multi tone communications such as equalizers, clock generators, clock and data recovery circuits, TISAR ADC’s, serialisers and output drivers etc.
Expertise in design and layout of high-speed circuits such as oscillators, phase-locked loops, delay-locked loops, and other fundamental building blocks like biasing, amplifiers, buffers, regulators, filters, ADC, DAC etc.
Experience with modern semiconductor process technologies, preferably in finFet technology nodes
Experience using Ocean, MDL or equivalent to automate analog design verification is highly desirable.
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