Design and optimize high-performance CPU microarchitectures for mobile, data center, and other applications
Develop and implement innovative microarchitecture techniques, analyze performance, and optimize SoC designs
Perform quantitative analysis of key mobile benchmarks and correlate with hardware performance monitoring unit (PMU) stats
Collaborate with cross-functional teams to develop and integrate system-on-chip (SoC) designs
Analyze and optimize CPU performance using top-down microarchitecture analysis methods
Extract and assess key microarchitecture ideas from open literature and apply them to designs
Write RTL code (Verilog or SV) and C/C++/Python scripts for performance evaluation of microarchitecture techniques
Requirements
15+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 13+ years of experience with a Master’s Degree, or 11+ years of experience with a Ph.D.
Strong fundamentals in key computer architecture concepts, such as virtual aliasing, pipelining, cache hierarchies, coherency, memory subsystem, etc.
Deep knowledge in high-performance OoO CPU microarchitecture and SOTA optimization techniques in key areas such as pipelining, interlock, caching, prefetching, branch prediction, cache/TLB hierarchy and their PPA implications
Ability to perform quantitative analysis of key mobile benchmarks such as Geekbench6 and SPECCPU17 and correlation with HW PMU stats (cache misses, TLB misses, pipeline stalls, etc.)
Extensive programming experience with RTL code (Verilog or SV), and writing C/C++/Python scripts, for performance evaluation of uarch techniques
Working experience with top-down microarchitecture analysis method (based on PMU stats)
Ability to extract and assess key uarch ideas in open literature
Strong communication and collaboration skills, with the ability to work effectively in a cross-functional team environment.
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