Power Delivery Solution Architect designing innovative chiplet - based power solutions for high - performance semiconductors. Engaging with customers to optimize power delivery network designs and enhance product development.

PowerLattice redefines how power enters into processors with its groundbreaking power delivery chiplets.
Combining on-die magnetic inductors, advanced micro-IVR circuits, a vertical design and a programmable software layer into a single chiplet die, PowerLattice enables the tightest coupling between power and compute, and delivers the breakthrough performance, efficiency and reliability for AI and data center infrastructure.
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Power Delivery Solution Architect designing innovative chiplet - based power solutions for high - performance semiconductors. Engaging with customers to optimize power delivery network designs and enhance product development.
Principal Digital Design Engineer at PowerLattice driving microarchitecture and design of complex digital systems for next - gen AI chips. Hands - on role blending technical leadership with RTL development in hybrid setting.
Senior or Staff Analog IC Designer developing analog and mixed - signal circuits for groundbreaking chiplet solutions at PowerLattice. Collaborating with cross - functional teams to deliver robust designs.
Staff Physical Design Engineer at PowerLattice implementing advanced SoC designs. Collaborating on floorplanning, routing, and physical verification for next - gen chiplet solutions.