Responsible for DFT (Design for Testability) aspects of ASIC Design
Thorough understanding of digital design concepts
Knowledgeable in the ASIC development process
Responsible for operating in a team environment and collaborate across different teams as required to accomplish the goals.
Requirements
Bachelor’s degree with 5 years of experience, a Master’s degree with 3 years of experience, or a Ph.D. with 1 year of experience in Science, Technology, Engineering, Mathematics, or related technical fields; an additional 4 years of experience may be considered in lieu of a degree.
U.S. Citizenship is required
Ability to obtain/maintain a clearance once hired
Experience in full product life cycle of ASIC Design
Experience with Cadence and/or Mentor test insertion and ATPG tools
Experience with hierarchical scan testing, IEEE-1500 and/or IEEE-1687, test compression, JTAG IEEE-1149.1 and IEEE-1149.6 (AC JTA)
Experience with memory BIST and logic BIST
Experience generating test patterns and analyzing and debugging test failures
Experience working with test engineers to implement ATPG vectors on tester hardware
Proficiency in HDL (VHDL/Verilog/SystemVerilog) and scripting languages such as Tcl, Python or Perl
Benefits
Health insurance coverage
Life and disability insurance
Savings plan
Company paid holidays
Paid time off (PTO) for vacation and/or personal business
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