Principal Engineer for ASIC SoC development at Micron Technology. Driving IP and SoC design for innovative memory and storage solutions with global team collaboration.
Responsibilities
Own end-to-end IP and SOC development from micro-architecture through RTL design, integration, and silicon support.
Own IP and Subsystem design from scratch, ensuring high-quality, reusable RTL.
Drive SoC integration, including CDC, lint, synthesis, STA, and power analysis.
Define and review module interfaces and system-level architecture.
Collaborate closely with Architecture, Verification, FW, DFT, Synthesis, and Physical Design teams.
Support post-silicon debug and bring-up activities.
Provide technical mentorship and participate in design and methodology reviews.
Requirements
12+ years of hands-on IP & SoC RTL design experience.
Strong expertise in micro-architecture, Verilog/System Verilog, and RTL integration.
Solid knowledge of asynchronous design concepts and CDC methodologies.
Deep understanding of SoC design flows (Lint, CDC, Synthesis/STA, Power).
Strong fundamentals in digital design and scripting languages.
Excellent problem-solving and communication skills.
Ability to work effectively with global cross-functional teams.
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