Hybrid Senior Application Support Engineer – Memory, eFUSE

at Intel Corporation

• Job title: Senior Application Support Engineer – Memory, eFUSE
• Job type: Full Time
• Experience level: Senior
• Salary: $141,910 - $269,100 per year
• Degree requirement: Bachelor's Degree
• Tech skills: Python
• Location requirements: Hybrid, Hillsboro, United States

About the role

• Senior Application Support Engineer at Intel Foundry focusing on customer support for memory and eFUSE technologies, collaborating across teams to drive improvements and documentation.

Responsibilities

• Act as the go-to technical expert for customers implementing FIP solutions, particularly Memory Compilers, Custom Memory, and eFUSE IP
• Take complete ownership of customer issues from initial report through resolution, including reproduction, analysis, debugging, and solution delivery
• Develop deep, strategic relationships with customers by understanding their design requirements, project timelines, and success metrics
• Partner with DTP teams to ensure seamless integration between FIP, PDKs, design flows, and signoff methodologies
• Work closely with R&D and QA teams to identify and resolve systemic issues, driving both immediate fixes and long-term improvements
• Serve as the customer advocate, translating customer needs into actionable requirements for product development teams
• Create comprehensive technical documentation including application notes, troubleshooting guides, and best practice recommendations
• Develop and deliver technical presentations for customers, partners, and internal leadership
• Support customer evaluation processes and production ramp activities to maximize success and minimize risk

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or STEM-related field
• 5+ years of combined Application engineering or customer support experience in one or more of these areas: Memory Compilers or Custom Memory solutions eFUSE or non-volatile memory IP Standard Cell Libraries or Analog/Mixed-Signal IP Design Automation focused on IP validation and integration
• Experience with SoC design flows (RTL through GDSII and signoff)
• Hands-on experience using at least one major EDA tool suites (Synopsys, Cadence, or Siemens EDA)
• Experience debugging complex design and EDA workflow issues with customer-focused prioritization
• Scripting experience, preferably in TCL and Python
• Experience with advanced process nodes (e.g., 7nm, 5nm, 3nm) and design-for-manufacturing considerations.

Benefits

• competitive pay
• stock bonuses
• health
• retirement
• vacation