Design Verification Engineer working on Block and Chip-Level ASIC verification at Cirrus Logic. Joining a world-class team in innovative solutions for consumer brands.
Responsibilities
Functional verification on custom mixed-signal ASICs
Developing detailed verification plans, methodology, and test-bench infrastructure
Developing constraint-random and directed tests, scoreboards, and checks
Coverage implementation, analysis, and closure
You will perform regression triage, failure analysis, and resolution
Running gate-level simulations, analyzing and resolving fails and timing violations
Working closely with digital/analog designers, systems, applications, and manufacturing test engineers to support both pre-silicon verification and post-silicon validation efforts
Requirements
Bachelor’s degree in Electrical or Computer Engineering and 7+ years of experience working on block-level or chip-level design verification for ASICs.
Strong background with HDLs (e.g. Verilog, VHDL) and HVLs (e.g. SystemVerilog/UVM, OVM, AVM, Vera)
Master’s degree in Electrical or Computer Engineering and 5+ years of experience working on block-level or chip-level design verification for ASICs.
Able to work closely with digital/analog designers, applications engineers, and manufacturing test to support both pre-silicon verification and post-silicon validation efforts
Knowledge of signal processing and Verilog Assertions
Ability to create, evaluate, debug, and improve verification processes
Ability to mentor junior engineers in verification methodology
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