Senior Layout Mask Design Engineer designing custom SRAMs for NVIDIA's future chips in advanced process technologies. Collaborating with teams on performance verification and layout methodologies.
About the role
- Perform physical implementation steps including floor planning, place and route, power/clock distribution, physical verification and timing closure at block level as well as full chip
- Work with logic designers & Hardware team to drive feasibility studies and explore design trade-off for physical design closure
- Perform technical evaluations of IP vendors, process nodes and provide recommendations
- Develop physical design methodologies and automation scripts for various implementation steps from Synthesis to GDSII
- Perform static timing analysis, create timing constraints and validation, critical path analysis, timing closure and timing sign-off
Requirements
- 5+ years of experience in ASIC physical design flow and methodologies in 3/5 and 7nm process nodes
- Has solid knowledge of full design cycle from RTL to GDSII and understanding of underlaying concepts of IC design, implementation flows and methodologies for deep submicron design
- Experience with EDA Place & Route tools like Fusion Compiler or Innovus or similar tools and Timing tools like Primetime or similar
- Scripting experience in TCL, python or Perl
- Candidates must have a bachelor's degree or higher in Electrical/Electronics and Communication/VLSI/Microelectronics with very good academics
Benefits
- Nokia offers continuous learning opportunities
- Well-being programs to support you mentally and physically
- Opportunities to join and get supported by employee resource groups
- Mentoring programs
- Highly diverse teams with an inclusive culture where people thrive and are empowered
Job title
Job type
Experience level
Salary
Not specified
Degree requirement
Tech skills
Location requirements
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