Hybrid Senior SerDes Architect – Lead

at Omni Design Technologies, Inc.

• Job title: Senior SerDes Architect – Lead
• Job type: Full Time
• Experience level: Senior
• Salary: Not specified
• Degree requirement: Bachelor's Degree
• Tech skills: DAC
• Location requirements: Hybrid, Milpitas, United States

About the role

• Senior SerDes Architect and development lead focusing on PAM4 ADC and DAC based technologies at Omni Design. Leading the transistor level design and market product introduction.

Responsibilities

• SerDes architect and development lead focused on PAM4 ADC and DAC based wireline technologies
• The successful candidate in this role will work with customers to understand requirements
• Will lead the development of high performance transistor level design starting from initial specification, through design and layout supervision, silicon evaluation and characterization to final product introduction to market

Requirements

• 10+ years of experience in high-performance analog or mixed-signal IC development in advanced CMOS processes
• Thorough familiarity with high-speed PAM4 architectures and topologies
• Experience in designing high performance building block circuits such as bandgap reference, op-amp, comparators, oscillators, DLL, PLL, CTLEs, CDRs, etc.
• Thorough understanding of equalization techniques (both analog and digital)
• Must have a track record of successfully taking designs to production
• Ability to work with customers to define products that address needs
• Must have experience with evaluating silicon on bench and familiarity with standard lab equipment
• Strong intuitive and analytical understanding of transistor-level circuit design including noise and mismatch analysis
• Experience with analog and digital behavioral modeling, and/or synthesis of digital control blocks
• Familiar with Cadence schematic capture, virtuoso, Spectre and/or HSPICE circuit simulation tools
• MATLAB understanding would be preferred but not mandatory
• Familiar with designing circuits for electromigration and ESD compliance in submicron CMOS process
• Must be familiar with layout parasitic extraction tools and layout dependent impairments in advanced CMOS processes
• Must be able to work independently, create and adhere to schedules
• Must possess strong written and verbal communication skills with an ability to work with teams spread across geographic locations
• Should be able to seek help proactively as well as share and pass on knowledge

Benefits

• excellent compensation