Hybrid Senior Physical Design Engineer, Clock Distribution

at Intel Corporation

• Job title: Senior Physical Design Engineer, Clock Distribution
• Job type: Full Time
• Experience level: Senior
• Salary: $161,230 - $303,140 per year
• Degree requirement: Bachelor's Degree
• Location requirements: Hybrid, Austin, United States

About the role

• Senior Physical Design Engineer at Intel focusing on clock architecture and design methodologies for innovative technology solutions. Collaborating with design teams to achieve performance and power goals in silicon design.

Responsibilities

• Defines and develops physical clock architecture, drives clocking designs, and creates clocking methodologies and guidelines for IPs or SoCs.
• Designs new clocks modules and circuit solutions and implements solutions that meet security and safety compliance for IP or SoC clocking.
• Defines SoC or subsystem level clocking targets and drives design teams to achieve these objectives as required.
• Build simulation models, drives physical implementation, conducts clock analysis, and supports power grid methodologies and implementation.
• Creates scalable flows for clocking infrastructure for better performance and power in the design.
• Interacts with architecture and IP/SoC design teams to understand clocking requirements and help them in deciding the right clock distribution methodology based on power and performance requirements.

Requirements

• Bachelor's Degree in Computer or Electrical Engineering or related field with 6+ years of relevant experience -OR- a Master’s Degree in Computer or Electrical Engineering or related field with 4+ years of relevant experience -OR- PhD in Computer or Electrical Engineering with 2+ years of relevant experience
• 2+ years of experience in synthesis, place and route static timing analysis using Primetime tools, DFT flows, and low power design
• Experience in Fusion Compiler and clock distribution tools such as Clock Builder.
• Experience as technical leader of SOC/ASIC designs responsible for planning design and physical convergence of SoC clock distribution.

Benefits

• competitive pay
• stock
• bonuses
• health
• retirement
• vacation