Develop system and/or FPGA architectures based on high level requirements.
Target device trade studies, recommendations, and selection
Requirements capture, ASIC / FPGA digital architecture and design using RTL, timing closure, verification, and system integration
Recommend new tools and practices for continuous improvement in the group's ASIC / FPGA design flow
Contribute to engineering estimates for new program pursuits.
May provide technical leadership for project design teams by breaking down work, planning activities, and reporting status
Requirements
Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and minimum 5 years prior relevant experience or an Advanced Degree in a related field and minimum 3 years of experience.
Demonstrated professional experience communicating in English (verbal and written).
U.S. citizenship is required, as only U.S. citizens are authorized to access information under this program/contract.
RTL coding and simulation in VHDL, Verilog, or SystemVerilog experience
Digital circuit architecture, design, resource trade-offs, timing analysis and timing closure
Testbench development for the verification of RTL blocks using VHDL or System Verilog.
Proficiency using ASIC and/or FPGA simulation and synthesis tools (e.g. Modelsim, Synplify, Quartus, Vivado, or other FPGA-specific tools)
Familiarity with revision control concepts and tools (e.g. Git, Subversion)
Familiarity with best practice chip-level verification techniques and languages (e.g. constrained random, functional coverage, SystemVerilog)
ASIC / FPGA lab validation with advanced lab equipment
Design for Test (DFT) and manufacturability issues
Experience with Unix, scripting, C/C++, and/or Perl
Benefits
Medical, dental, and vision insurance
Three weeks of vacation for newly hired employees
Generous 401(k) plan that includes employer matching funds
Participation in the Employee Scholar Program (ESP)
Life insurance and disability coverage
Employee Assistance Plan, including up to 8 free counseling sessions.
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