Onsite Senior STA Engineer, Sub-chip

Posted 7 hours ago

Apply now

About the role

  • Physical Design Engineer at NVIDIA focusing on advanced Static Timing Analysis. Collaborating with teams to ensure timing convergence and quality approval throughout project stages.

Responsibilities

  • Perform advanced Static Timing Analysis (STA) for HSIO at chiplet and FC level
  • Running Prime Time, review and debug timing paths, understand constraints, sdc generation, timing ecos generation
  • Identify convergence risks and work closely with physical design, RTL and DFT teams, ensuring convergence throughout various project stages
  • Responsible for a full timing closer and quality approval from pre-layout STA model through signoff
  • AI use for timing optimization and data analysis

Requirements

  • B.SC./ M.SC. in Electrical Engineering
  • At least 5+ years of hands-on STA experience
  • Experience in Prime Time and signoff methodologies
  • AI tools orientation or alternatively a desire to learn
  • Experience in Linux environments
  • TCL, Python, shell scripting abilities
  • Experience with data collection and analysis

Benefits

  • Health insurance
  • Professional development

Job title

Senior STA Engineer, Sub-chip

Job type

Experience level

Senior

Salary

Not specified

Degree requirement

Bachelor's Degree

Location requirements

Report this job

See something inaccurate? Let us know and we'll update the listing.

Report job