Hybrid Senior Physical Design Engineer – Circuits

at NVIDIA

• Job title: Senior Physical Design Engineer – Circuits
• Job type: Full Time
• Experience level: Senior
• Salary: $168,000 - $264,500 per year
• Degree requirement: Bachelor's Degree
• Tech skills: Perl, Python
• Location requirements: Hybrid, Santa Clara, United States

About the role

• Senior Physical Design Engineer for GPU and ASIC physical designs. Collaborating with global teams to innovate in hardware security and power management solutions.

Responsibilities

• Work as part of a global circuits team alongside custom circuit designers and custom mask designers to deliver physical designs of innovative circuits for hardware security, adaptive clocking, and power management solutions.
• Responsible for all aspects of physical design and implementation of custom macros for GPU and other ASICs targeted at the desktop, laptop, workstation, and mobile markets.
• Lead all custom circuit IP level PD activities for the macros assigned to you.
• Drive the physical implementation of custom mixed signal IPs using industry standard tools and novel custom AI automated place and route tools.
• Participate in establishing physical design methodologies, flow automation, floorplan, power/clock distribution, custom IP P&R, and timing closure.
• PD activities include floor plans, abstract view generation, RC extraction, PNR, STA, EM,IR DROP, DRCs & schematic to layout verification.
• Work in collaboration with design team to address design challenges.

Requirements

• BSEE (MSEE preferred) or equivalent experience.
• 6+ years of experience in large VLSI physical design implementation on 5nm, 4nm and/or 3nm technology.
• Successful track record of delivering designs to production is a requirement.
• Good understanding of the RTL2GDSII concepts related to synthesis, place & route, CTS, timing convergence, layout closure.
• Good knowledge and experience in Block-level Floor-planning and Physical verification.
• Working experience with tools like ICC2/Innovus, Primetime/Tempus etc used in the RTL2GDSII implementation.
• Strong knowledge and experience in standard place and route flows ICC2/Synopsys and Innovus/Cadence flows preferred.
• Well versed with timing constraints, STA, and timing closure.
• Good automation skills in Python, PERL, TCL, tool specific scripting on one of the industry leading Place & Route tools.
• Proficiency using Perl, Tcl, Make scripting is preferred.

Benefits

• equity
• benefits