Senior Package Layout Engineer at NVIDIA collaborating on high speed ASIC package designs. Involves layout development, team collaboration, and design optimization for advanced technologies.
Responsibilities
Collaborate with Technical Package Lead and different design teams
Implement high speed/density ASIC packages
Perform substrate breakout patterns for ASIC packages
Optimize package pinout incorporating system level trade-offs of pins assignment
Help perform package routing, placement, stack-up, reference plane and power distribution using Cadence APD or SiP tool suite
Propose layout design trade-offs to the Technical Package Lead for resolution and implementation
Conduct design feasibility studies to evaluate the Package design goals for size, cost, and system performance
Develop symbols and CAD library databases using Cadence APD design tools
Develop methodologies to improve layout productivity
Requirements
Hold a B.S. Electrical Engineering or equivalent experience
5+ years experience in PCB Layout of graphics cards, motherboards, line cards or other related technology.
Experience with HDI designs is a plus
Proven experience in substrate layout of wire bond and flip chip packages, preferred
Significant background with Cadence APD or SiP and/or PCB layout tools (including Constraint Manager)
Solid understanding of high-speed design signal integrity practices
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