Senior ASIC Design Engineer at NVIDIA implementing high performance and power efficient RTL design. Collaborating with diverse teams to push the frontiers of computing innovation.
Responsibilities
Implement, document and deliver high performance, area and power efficient RTL to achieve design targets and specifications
Analyze architectural trade-offs based on features, performance requirements and system limitations
Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis/timing clean design
Collaborate and coordinate with architects, other designers, pre- and post-silicon verification teams, synthesis, timing and back-end teams
Work on critical designs which are integral to our LLM performance such as real-time numeric processing, data flow processing, interrupt controllers, and DMA engines
Architect features to help silicon debug and support post-silicon validation activities
Requirements
Bachelors Degree or equivalent experience in Electrical Engineering, Computer Engineering or Computer Science
8+ years of relevant work experience
Experience in micro-architecture and RTL development (Verilog), focused on arbiters, scheduling, synchronization & bus protocols and interconnect networks
Great understanding of ASIC design flow including RTL design, verification, logic synthesis, low-power design and timing analysis
Exposure to Digital systems and VLSI design, Computer Architecture, and Computer Arithmetic is required
Specific knowledge in numerics, confidential compute, dataflow architectures and CPU subsystems is a bonus
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