Design Verification Engineer at Marvell validating circuitry for semiconductor solutions. Developing verification environments and ensuring chip designs meet customer specifications.
Responsibilities
verify all of the circuitry that goes inside our chips for the general market and for specific customers
develop the architecture for a functional verification environment, including reference models and bus-functional monitors and drivers
writing a verification test plan using random techniques and coverage analysis and working with designers to ensure it is complete
developing tests and tuning the environment to achieve coverage goals
debugging failures and working with designers to resolve issues
verifying boot code and architecting, developing, and maintaining tools to streamline the design of state-of-the-art multi-core SoCs
transforming the requirements from the engineering teams into software tools that are both easy to use and scalable within a highly parallel compute environment
unit and regression testing of software tools
Requirements
BS Computer Engineering, Electrical Engineering, or Computer Science with 10+ years of verification and firmware and software development experience (or MS/PhD with 5+ years experience)
Experience with System Verilog, UVM
Experience with writing a detailed test plan and building a sophisticated, directed, random-verification environment
Experience with scripting language such as Python or Perl and EDA Verification tools
Experience with Object-Oriented Design and implementation
Good understanding of Linux O.S.
Good programming skills desired, especially C++ and ARM assembly
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