Modeling Engineer at Kandou implementing software for system - level modeling of communication links. Collaborating with architects and verification teams to define and support designs.
About the role
- Digital Verification Engineer developing verification methodologies and validating circuit designs for Kandou's AI hardware. Ensuring timely project completion and utilizing latest verification techniques.
Responsibilities
- Develop design verification methodologies and implement standard debug flows
- Work with designers in verification and validation of circuit designs
- Participate in design reviews
- Prepare design verification plan based on design specifications
- Plan and schedule assigned projects for timely completion
- Utilize the latest techniques, tools, and technologies for design verification activities
- Maintain design verification environment and track & close design bugs
Requirements
- 5+ years’ experience in the semiconductor industry
- Proven track record in verifying complex designs (preferably in high volume applications) - FPGA or ASIC
- Skilled in trade-offs between quality and schedule
- Experience in constrained random test bench development
- Familiarity with SerDes and high-level protocols (e.g., PCle, USB, DP) would be advantageous
- Extensive digital verification background with some UVM experience
- Bachelor of Engineering in Electronics and Electrical Engineer (equivalent or higher)
Job title
Job type
Experience level
Salary
Not specified
Degree requirement
Location requirements
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