Hybrid DFT Engineer

at Kandou

• Job title: DFT Engineer
• Job type: Full Time
• Experience level: Mid level, Senior
• Salary: Not specified
• Degree requirement: Bachelor's Degree
• Location requirements: Hybrid, Hyderabad, India

About the role

• DFT Engineer working on chiplet-based AI memory fabric solutions at Kandou, collaborating with test and production engineering teams for debugging.

Responsibilities

• Hierarchical MBIST and scan insertion, BSD implementation ATPG pattern generation, coverage analysis, converging to high coverage metrics
• Pattern simulations with timing
• Defining test mode timing constraints, analyzing the timing reports and converge timing
• Developing cycle accurate functional patterns using IJTAG methodology
• Closely working with the test and production engineering teams to debug and bring up devices at probe and final test
• Debugging silicon issues

Requirements

• 5+ years of DFT experience including implementation, test pattern development, and simulation
• Proven experience in contributing to DFT solution to complex designs
• Experience working with IJTAG methodologies
• Experience with hierarchical MBIST insertion, hierarchical scan insertion and scan compression methodologies
• Experience in ATPG pattern generation for different kinds of fault models, fault coverage analysis and converging to high coverage metrics
• Good debug capabilities in simulating patterns with timing
• Experience with industry standard EDA tools for DFT, timing, and simulation
• Knowledge of System Verilog