Sr. IP Logic Design Engineer responsible for architecting memory coherency protocols and circuits for AI SoCs. Collaborating with cross-functional teams to ensure system optimization in data centers.
Responsibilities
Architect scalable memory coherency protocols and interconnect topologies for high performance and low latency for data center and AI SoCs
Design and implement critical components of the memory fabric microarchitecture
Develop RTL code for core components of the memory fabric
Work with verification teams to create test plans and debug issues
Collaborate with cross-functional teams for seamless integration of memory fabric systems
Analyze system performance and optimize the architecture for target use cases
Mentor junior engineers and contribute to technical reviews and design documentation
Stay updated with technologies and trends in memory subsystems, coherency protocols, and AI/ML hardware
Requirements
MS/PhD in Electrical Engineering, Computer Engineering, or related field
10+ years in SoC design, including significant experience in memory systems, coherency protocols, and RTL coding
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