Hybrid Senior IP Logic Design Engineer

Posted 2 hours ago

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About the role

  • Sr. IP Logic Design Engineer responsible for architecting memory coherency protocols and circuits for AI SoCs. Collaborating with cross-functional teams to ensure system optimization in data centers.

Responsibilities

  • Architect scalable memory coherency protocols and interconnect topologies for high performance and low latency for data center and AI SoCs
  • Design and implement critical components of the memory fabric microarchitecture
  • Develop RTL code for core components of the memory fabric
  • Work with verification teams to create test plans and debug issues
  • Collaborate with cross-functional teams for seamless integration of memory fabric systems
  • Analyze system performance and optimize the architecture for target use cases
  • Mentor junior engineers and contribute to technical reviews and design documentation
  • Stay updated with technologies and trends in memory subsystems, coherency protocols, and AI/ML hardware

Requirements

  • MS/PhD in Electrical Engineering, Computer Engineering, or related field
  • 10+ years in SoC design, including significant experience in memory systems, coherency protocols, and RTL coding
  • Expertise in memory coherency protocols (e.g., MESI, MOESI, CXL, CCIX, CHI)
  • Strong knowledge of interconnect technologies (e.g., AMBA, PCIe, NoC architectures)
  • Proven RTL coding experience in Verilog or SystemVerilog
  • Proficiency in simulation tools for performance modeling and analysis
  • Familiarity with physical design implications of memory fabric architectures (timing, power, area)
  • Experience with EDA tools for synthesis, linting, and static timing analysis
  • Hands-on experience with high-bandwidth memory (HBM), DDR, or other advanced memory technologies
  • Background in AI/ML accelerator or data center SoC design
  • Knowledge of scripting languages like Python or TCL for workflow automation
  • Experience with software-hardware co-design for end-to-end system optimization
  • Strong problem-solving and debugging skills
  • Excellent communication and collaboration abilities
  • Ability to manage and prioritize multiple tasks effectively

Benefits

  • Competitive pay
  • Stock bonuses
  • Benefit programs including health, retirement, and vacation

Job title

Senior IP Logic Design Engineer

Job type

Experience level

Senior

Salary

$190,610 - $269,100 per year

Degree requirement

Postgraduate Degree

Tech skills

Location requirements

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