RTL Design Engineer developing logic design and RTL coding for SoC designs at Intel. Responsibilities include verifying designs and integrating components for AI applications in a collaborative environment.
Responsibilities
Develop logic design, register transfer level (RTL) coding, and simulation for SoC designs
Integrate IP blocks and subsystems into full chip SoC or discrete component designs
Define architecture and microarchitecture features of the blocks being designed
Perform quality checks across various logic design aspects ranging from RTL to timing/power convergence
Apply various strategies, tools, and methods to write RTL and optimize logic to meet power, performance, area, and timing goals
Review verification plans and implementation to ensure design features are verified correctly
Resolve and implement corrective measures for failing RTL tests
Follow secure development practices to address security threat models and objectives within the design
Drive quality assurance compliance for smooth IP/SoC handoff
Requirements
Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science
4+ years of experience in/with: RTL design and implementation for ASIC/SoC development
Proficiency in Verilog/SystemVerilog for RTL coding and design
Experience with synthesis tools and timing closure methodologies
Understanding of clock domain crossings, power optimization, and timing closure (Preferred)
Exposure to SoC system integration and CPU subsystem design (Preferred)
Familiarity with standard bus protocols (AXI, AHB, etc.) and embedded processor architectures (Preferred)
Knowledge of high-speed and low-power design techniques (Preferred)
Experience with static timing analysis (STA) tools and methodologies (Preferred)
Hands-on experience with formal verification tools and techniques (Preferred)
Basic scripting skills (Python, TCL, etc.) for automation (Preferred)
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