Senior Silicon Validation Engineer validating high-performance interconnects for HPC and AI clusters at HPE. Leading team and developing tests for silicon validation in a dynamic environment.
Responsibilities
Oversees full chip-level validation, utilizing emulators and developing tests that run at the operating system level to assess both HPE Slingshot and industry standard networking protocols.
Provides technical leadership for the HPE Slingshot Silicon Validation engineering team, responsible for all stages of ASIC validation for Network Interface Cards (NIC) and Switch hardware.
Owns the validation strategy and risk management for major projects.
Drives innovation and integration of new technologies and methodologies into Silicon Validation projects and activities.
Provides input on the selection and development of future technical leaders.
Mentors and develops less experienced staff members, setting an example of innovation and excellence in Silicon Validation.
Collaborates and communicates with management and internal partners regarding validation status, project progress, and issue resolution.
Requirements
Bachelor’s or master’s degree in electrical engineering, computer engineering, computer science or equivalent.
6-10+ years of experience in VLSI Validation, verification, or design, including experience leading teams or complex projects.
Senior level proficiency in object-oriented Python programming
Senior level proficiency in Linux command line, Verilog hardware description language, electronic design automation (EDA)
Demonstrated ability to rapidly acquire and apply new technical knowledge in a dynamic and geographically diverse work environment.
Senior level experience in ASIC Silicon Validation and testing is required.
Senior level knowledge of industry standard networking protocols is required. (200G/400G/800G+ Ethernet, 50G/100G/200G+ SERDES (Die to Die as well as long reach))
Executive written and verbal communication skills; mastery in English.
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